Radix-4 multiplier with regular layout structure - Electronics Letters

pump boosting circuit, one PLL with a charge pump boosting circuit and another one without a boosting circuit (the same as the conventional PLL) have been implemented in a 0 . 8 ~ CMOS technology. Fig. 3 shows the maximum frequency to which both PLLs can lock with a supply voltage change. The proposed PLL can be locked to 672MHz at 3.3V supply, which is 1.9 times the maximum frequency of the conventional PLL. The jitter measurement results are as follows. When the supply noise is not injected, the rms jitter is 8.3ps and the peak-to-peak jitter is 56ps. When 0.6V peak-to-peak supply noise is superposed with Vdd, the rms jitter is 67ps and the peak-to-peak jitter is 270ps when the operating frequency is < 592MHz. When the operating frequency is > 592MHz, the source follower enters the linear region. As the PLL does not have enough noise margin at that condition, the jitter becomes larger abruptly, resulting in 161ps (rms) and 512ps (peak-to-peak) jitter.